TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs

The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance sorting acceleration on FPGAs, which was conventionally bounded by available off-chip bandwidth. However, it is nontrivial for designers fully utilize this immense First, existing sorter designs cannot be directly scaled at increasing rate bandwidth, as required on-chip resource usage grows a much faster and would bound in turn. Second, need an in-depth understanding HBM's characteristics effectively HBM To tackle these challenges, we present TopSort, novel two-phase solution optimized HBM-based FPGAs. In first phase, 16 merge trees work parallel 32 channels' second TopSort reuses logic from phase one form wider tree partially sorted results one. also adopts HBM-specific optimizations reduce overhead improve bandwidth utilization. can sort up 4 GB data using all channels, with overall 15.6 GB/s. 6.7× 2.7× than state-of-the-art CPU FPGA sorters.